The ever growing demand for more bandwidth in telecom, datacom and in data center (computercom) applications has led to various attempts to improve the efficiency of optical transmitter-receiver (transceiver) devices which are the building blocks of optical interconnects. Typical applications are found in high performance computing, storage servers, switches and routers. Common to all of these applications is the need to route data between several application specific integrated circuits (“ASIC”), usually processors or memory.
To facilitate an optical interconnect, the transceiver module must be electrically coupled to the ASIC chip which is handling the logic tasks of a specific application. Efficient packaging and thermal relief system are thus needed especially when the transceiver is physically located on the ASIC. Optical interconnection between various chips can be carried out using any optical routing technique, for example, fiber optics, waveguides or free space propagation. The required high efficiency is achieved by employing parallel optical links in the form of two-dimensional optoelectronic matrices usually consisting of vertical cavity surface emitting lasers (VCSEL) and matrices of p-i-n photodiodes (PD).
Practical realization of dense optical interconnect is limited due to the fact that industry standard optoelectronic devices are based on one-dimensional, 1×12 arrays of VCSEL and PD. This limits the number of channels that can be used in a practical device. Additionally, the analog circuitry required to drive these optoelectronic chips is typically not monolithically integrated but rather assembled adjacent to the chips and connected either by wire bonds or via an interposer chip. Such complications limit the usefulness of optical interconnects leading to low utilization of the device area. Utilizing large, two-dimensional (2D), optoelectronic devices and packaging the analog circuitry in a space-efficient manner can increase the bandwidth per unit area.
U.S. Pat. No. 7,702,191 discusses a method of assembling large, two-dimensional, optoelectronic chips on an ASIC chip, the contents of which are incorporated herein in their entirety. This application uses a different method for attaching the optical routing elements to the device.